低抖动,10输出MEMS抖动清洁器

TheCascade™SiT95145 is a single-chip MEMS jitter cleaner that provides the highest level of clock tree integration and consolidates multiple clock ICs and oscillators into a single device. Its low noise quad-PLL architecture and programmable output drivers provide up to 10 differential or 20 LVCMOS low-jitter clock outputs. It supports 4 additional clock inputs with Frac-N dividers, enabling virtually any input-to-output frequency translation configurations from 8 kHz to 2.1 GHz.

This jitter cleaner integrates SiTime’s third-generation MEMS resonator. This integrated MEMS approach eliminates the dependency on a crystal reference, along with all quartz related issues. It enables a true clock-system-on-a-chip that improves system robustness:

  • Always-accurate clock synthesis by eliminating crystal capacitive mismatch
  • Always-reliable startup even at cold temperature and other harsh environmental conditions
  • No jitter degradation due to noise coupling onto a crystal interface
  • 没有活动倾斜/频率跳跃到石英固有
  • 10倍的抗振动和弯曲

Timemaster™软件支持S亚博电竞IT95145,以简化时钟树设计。该设备还可以附带用户指定的工厂预编程默认启动配置。可以通过I2C / SPI在制造或配置期间使用两个一次可编程(OTP)内存的两个银行来重新编程两次设备配置,以通过I2C / SPI进行额外的BOM灵活性。SIT95145也得到了支持亚博电竞SiT6503EB评估板。

Single-chip MEMS jitter cleaner consolidates MEMS resonator, multiple clock ICs and oscillators into a single  9 x 9 mm 64-pin device
输入数量 4
Number of Outputs 10.
Input Frequency Range 8 kHz至2.1 GHz(差速器),8 kHz至250 MHz(LVCMOS
Output Frequency Range 8 kHz至2.1 GHz(差速器),8 kHz至250 MHz(LVCMOS),1 PPS(仅一次输出)
Output Type LVPECL, CML, HCSL, LVDS, LVCMOS
Number of PLL/Clock Domains 4 PLL,1个时间域
可编程环路带宽 1 MHz至4 kHz
Operating Temperature Range (°C) -40 to +85
Phase Jitter (rms) 120 FS.
电压电源(V) 1.8,2.5,3.3
Operating Mode 自由运行,同步,保持
Package Type (mm²) 9x9 mm, 64-pin
特征 Hitless switching, zero-delay buffer mode, DCO with 50-ppt resolution, programmable output delay control
可用性 采样

Clock-system-on-a-chip with integrated MEMS, simplifies designs

  • 没有晶体容量匹配问题,始终准确的频率合成
  • No noise coupling onto crystal circuits, guaranteed jitter
  • Resistant to vibration and board bending, anywhere PCB placement

Flexible features for the highest level of clock consolidation

  • 4输入,10个输出,4个PLL,高达2.1 GHz输出频率,用于灵活频率转换
  • 可单独的可配置输出类型和电压,以支持各种处理器和SOC亚博电竞
  • Programmable loop bandwidth (1 mHz to 4 kHz)

35%的空间可节省高密度设计的理想选择

  • 9 x 9 mm包,无需外部XTAL /振荡器

半导体级质量和可靠性,消除了与传统时钟相关的石英相关问题

  • Low jitter clock frequency translation and generation
  • Clock tree consolidation replacing crystal oscillators (XOs) and buffers
  • 10.G/100G/400G Ethernet clocking
  • Synchronous Ethernet (G.8262, options 1 and 2)
  • Optical transport network (OTN) clocking for framers, mappers, and processors
  • FPGA, processor, and memory clocking
  • Storage, servers and datacenters
  • Test and measurement
  • Broadcast video

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Document Name Type
SINTIME产品的制造票据 Other Quality Documents

SiT6503 Eval Board User Manual- 评估设备性能

时钟软件的TimeMaster(Contact SiTime)- 简化时钟树设计

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