Low Jitter, 10-output MEMS Clock Generator

The Cascade™ SiT95141 is a single-chip MEMS clock generator optimized for the highest level of clock tree integration. This clock-system-on-a-chip (ClkSoC) consolidates multiple clock ICs and oscillators into a single device. Its low noise quad-PLL architecture and programmable output drivers provide up to 10 differential or 20 LVCMOS low-jitter clock outputs. It supports 4 additional clock inputs with Frac-N dividers, enabling virtually any input-to-output frequency translation configurations from 8 kHz to 2.1 GHz.

This clock generator integrates SiTime’s third-generation MEMS resonator. This integrated MEMS approach eliminates the traditional clock dependency on crystal reference and quartz related issues, and improves system robustness:

  • Always accurate clock synthesis by eliminating crystal capacitive mismatch
  • 即使在寒冷的温度和其他恶劣的环境条件下,始终可靠启动
  • 由于噪声耦合到晶体界面上没有抖动降级
  • 无活动倾斜/频率跳跃与Quartz固有
  • 10x更耐振动和板弯曲

The SiT95141 is supported by TimeMaster™ software that simplifies clock tree design. The device can also be shipped with a user-specified, factory pre-programmed default startup configuration. The device configuration can be re-programmed twice using two banks of one-time-programmable (OTP) memory during manufacturing or configured in-system via I2C/SPI for additional BOM flexibility.SIT95141也得到支持亚博电竞SiT6503EBevaluation board.

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单芯片时钟发生器将MEMS谐振器,多个时钟IC和振荡器整合到单个9 x 9 mm 64引脚设备中
Number of Inputs 4.
Number of Outputs 10
输入频率范围 8 kHz 2.1 GHz(微分),8千赫至250 MHz(LVCMOS)
Output Frequency Range 8 kHz 2.1 GHz(微分),8千赫至250 MHz(LVCMOS), 1 PPS (one output only)
输出类型 LVPECL, CML, HCSL, LVDS, LVCMO
Number of PLL/Clock Domains 4.PLL, 1 time domain
工作温度范围(°C) -40到+85
阶段抖动(RMS) 120 fs
Voltage Supply (V) 1.8, 2.5, 3.3
Operating Mode 自由运行,同步
Package Type (mm²) 9x9 mm,64针
Features Redundant clock inputs with manual switching, DCO mode via I2C or SPI, 5 ppt resolution, programable output delay control
可用性 采样

Clock-system-on-a-chip with integrated MEMS, simplifies designs

  • No crystal capacity matching issues, always accurate frequency synthesis
  • No noise coupling onto crystal circuits, guaranteed jitter
  • 耐振动和板弯曲,任何地方PCB放置

Flexible features for the highest level of clock consolidation

  • 10输出,4个独立PLL,最大为2.1 GHz输出频率,可用于最大频率敏捷性
  • 可单独配置的输出类型和电压,以支持各种处理器和SOC亚博电竞
  • Optional 4 inputs to enable flexible input-output frequency translation
  • In-system programmability via I2C or SPI for further SKU reduction

35% space saving, ideal for high density designs

  • 9 x 9 mm package, no external XTAL/oscillator required

Semiconductor level quality and reliability, eliminates quartz-related issues associated with traditional clocks

  • 时钟树整合更换晶体振荡器(XOS)和缓冲区
  • Low jitter clock frequency translation and generation
  • 10G/100G/400G Ethernet clocking
  • Optical transport network (OTN) clocking for framers, mappers, and processors
  • FPGA,处理器和内存时钟
  • 存储,服务器和数据中心
  • Test and measurement
  • Broadcast video

SiT6503EB Evaluation BoardUser Manual

时钟软件的TimeMaster- 简化时钟树设计(联系Silime.

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