Low Jitter, 11-output MEMS Clock Generator

The Cascade™ SiT95143 is a single-chip MEMS clock generator optimized for the highest level of clock tree integration. This clock-system-on-a-chip (ClkSoC) consolidates multiple clock ICs and oscillators into a single device. Its low noise quad-PLL architecture and programmable output drivers provide up to 10 differential or 20 LVCMOS low-jitter clock outputs. It supports 4 additional clock inputs with Frac-N dividers, enabling virtually any input-to-output frequency translation configurations from 8 kHz to 2.1 GHz.

This clock generator integrates SiTime’s third-generation MEMS resonator. This integrated MEMS approach eliminates the traditional clock dependency on crystal reference and quartz related issues, and improves system robustness:

  • Always accurate clock synthesis by eliminating crystal capacitive mismatch
  • Always reliable startup even at cold temperature and in other harsh environmental conditions
  • No jitter degradation because of noise coupling onto a crystal interface
  • 没有活动下降/跳跃固有频率与必要rtz
  • 10倍的抗振动和弯曲

SiT95143由定时器支持™ 亚博电竞简化时钟树设计的软件。该设备也可以随附用户指定的出厂预编程默认启动配置。在制造过程中,可以使用两组一次性可编程(OTP)存储器对设备配置进行两次重新编程,或者通过I2C/SPI在系统中进行配置,以增加BOM灵活性。SiT95143还支持SiT6503EBevaluation board.

Single-chip clock generator consolidates MEMS resonator, multiple clock ICs and oscillators into a single 9 x 9 mm 64-pin device
Number of Inputs 4
输出数量 11
Input Frequency Range 8 kHz to 2.1 GHz (differential), 8 kHz to 250 MHz (LVCMOS)
输出频率范围 8 kHz to 2.1 GHz (differential), 8 kHz to 250 MHz (LVCMOS), 1 PPS (one output only)
PLL/时钟域数 4 PLL, 1 time domain
Operating Temperature Range (°C) -40 to +85
Phase Jitter (rms) 120 fs
Voltage Supply (V) 1.8, 2.5, 3.3
操作模式 Free running, synchronized
包装类型(mm²) 9x9 mm, 64-pin
Features Redundant clock inputs with manual switching, DCO mode via I2C or SPI, 5 ppt resolution, programmable output delay control
Availability Sampling


  • 无晶体容量匹配问题,频率合成始终精确
  • 无噪声耦合到晶体电路,保证抖动
  • Resistant to vibration and board bending, anywhere PCB placement


  • 11 outputs, 4 independent PLLs, up to 2.1 GHz output frequency for maximum frequency agility
  • Individually configurable output types and voltage to support a wide range of processors and SOCs
  • Optional 4 inputs to enable flexible input-output frequency translation
  • 通过I2C或SPI进行系统内编程,进一步减少SKU

35% space saving, ideal for high density designs

  • 9 x 9 mm package, no external XTAL/oscillator required

Semiconductor level quality and reliability, eliminates quartz-related issues associated with traditional clocks

  • Clock tree consolidation replacing crystal oscillators (XOs) and buffers
  • 低抖动时钟频率转换与产生
  • 10G/100G/400G以太网时钟
  • 为成帧器、映射器和处理器提供的光传输网络(OTN)时钟
  • FPGA, processor, and memory clocking
  • Storage, servers and datacenters
  • 测试和测量
  • 广播视频

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Manufacturing Notes for SiTime Products Other Quality Documents

SiT6503EB Evaluation BoardUser Manual

TimeMaster for Clocks Software-- Simplifies clock tree design (Contact SiTime)

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