是。用我们在线交叉参考工亚博国际老虎机游戏平台具。如果您需要额外的帮助，请联系您当地的sales representativespecifying the part number of the quartz XO including preferred package, operating temperature range, and VDD.

等效的距离围系SIT1602和SIT800X可以取代所有Sillabs CMEMS振荡器。可以找到这个家庭的数据表here。

所有Discera单端（SE）振荡器都可以由列出的inviee se等效部分取代here。
All Discera differential-ended (DE) oscillators can be replaced by SiTime DE equivalent parts listedhere。

是。All SiTime products are RoHS certified.

请访问quality and reliabilitysection of the website. You will need to be a注册user to download documents from this section.

不，他们不是。

"Activity dips" are defined as abrupt changes of frequency in a quartz crystal-based oscillator. A crystal-based oscillator may often exhibit an activity dip at critical temperatures, and return just as abruptly to normal behavior for small deviations of temperature away from the critical value.

The most common causes of activity dips are:

1. “耦合模式” - 不同温度系数的不同晶体振荡模式的碰撞。
2. 水晶包装内的湿度冷凝到石英板上。

All of these effects can rob the main oscillation mode of energy, effectively causing the crystal to drop out of oscillation or to oscillate temporarily in a different crystal mode.

基于境内MEMS的振荡器不受这些效果的影响：

1. sitMEMS oscillation modes are primarily determined by the material properties of silicon; all modes or spurious response characteristics change with temperature in exactly the same manner as the fundamental oscillation mode. Therefore, different modes can never interact at the same frequency and cause a dip.
2. sit's MEMS First™ process uses standard silicon fabrication techniques to hermetically seal the MEMS in a very high-temperature, clean, vacuum environment. This creates an extremely clean, moisture-free environment for the MEMS, and eliminates the possibility of contaminant- or moisture-induced activity dips.

situses industry standard processes to conduct reliability qualifications of products using accelerated life cycle stress tests like HTOL.

The key reliability metric SiTime publishes is the FIT or (Failure in Time) which provides an estimate of the expected number of device failures after 1 billion hours of operation. A related metric is MTBF (Mean Time between Failure) which is the inverse of FIT.

其他可靠性指标是：
EFR – Early Failure Results
ESD - Electrostatic discharge
陆-封闭
MS - 机械冲击
VFV – Variable Frequency Vibration
VF - 振动疲劳
CA – Constant Acceleration

所有恒星产品都是使用我们强大的6秒形工艺设计和带入生产的。产品完全有特色和合格的JEDEC和AEC标准。为了确保最高质量，Sentime在每个生产批次的零件样本上的温度范围内执行批量验收测试（LAT）。

sit's extremely high quality has been proven over shipment of hundreds of millions of units. Our actual field returns rate is less than 2 DPPM, which is amongst the best in the semiconductor industry. After more than six years of shipments, SiTime has had zero MEMS field failures.

FIT (Failure in Time) is a statistically extrapolated value based on accelerated testing (JEDEC22-A108) and applying acceleration factors based on failure modes on the tested devices. The difference in FIT rate across various products is due to different number of devices hours each product was stress tested to. The FIT numbers are reported when the reliability report is generated. Please refer to the latest reliability reports for the latest FIT values. //www.lzhylxs.com/support/quality-and-reliability#magictabs_eDH8P_3.

所有境内产品均有相同的底层技术和过程。截至2015年10月，境内应力测试了数千个振荡器，累计测试时间为3,307,000个没有故障的设备，导致计算拟合值为0.88或MTBF，1,140万小时。

sitMEMS oscillators are built with a MEMS resonator and CMOS die using standard semiconductor packaging processes. Since there has been no MEMS resonator failures among the > 250 million products shipped to date, we cannot compute the Activation Energy (Ea) for MEMS. Hence we use the industry standard Ea = 0.7 eV for CMOS as the Ea for the product. We are using the Ea of the worst case element of the device as the Ea for computing the reliability metric, FIT and MTBF for our products. For more details on how we compute the FIT/MTBF values please refer to application noteReliability Calculations for SiTime Oscillators。

One of the key elements enabling extremely stable MEMS resonators is SiTime’s EpiSeal™ process which hermetically seals the resonators during wafer processing, eliminating any need for hermetically sealed ceramic packaging. SiTime’s EpiSeal resonator is impervious to the highest concentration elements in the atmosphere, nitrogen and oxygen, and therefore acts as a perfect seal. Previous generations of EpiSeal resonators may have been impacted by large concentrations of小分子gas. Newer EpiSeal resonators are impervious to all小分子gases. Please contact SiTime in case you are planning to use a SiTime device in large concentrations of小分子gas, so that we can recommend an appropriate, immune part.

Sentime MEMS振荡器旨在为EMI实现一流的弹性。在应用笔记中记录了EMI易感性（EMS）的行业标准测量和性能图Electromagnetic Susceptibility Comparison of MEMS and Quartz-based Oscillators。

sitMEMS oscillators are designed to be less vibration sensitive and extremely shock resistant than similar quartz parts. They are designed to exhibit best-in-class resiliency to shock and vibration, and the industry standard measurements and performance plots for shock and vibration are documented in application noteShock and Vibration Comparison of MEMS and Quartz-based Oscillators.

MHz振荡器的电源噪声灵敏度（PSNR）在指定噪声频率的每MV电源噪声引起的抖动量方面被量化。SITIME MEMS MHz振荡器设计用于每MV为0.21 PS集成相位抖动（12 kHz至20 MHz）的频率为10kHz至20 MHz的频率为低至0.21ps集成的相位抖动（12kHz至20 MHz）。

Power Supply Noise Sensitivity (PSNR) for kHz oscillator families (SiT153x, SiT1552, SiT1630) is quantified in terms of frequency deviation with 300mV peak-to-peak sinusoidal noise injection across the frequency range of 10 KHz to 10 MHz. The PSNR plot for the above oscillator families is provided in the individualdatasheets。

sitrecommends using 100 ms or larger gate time with high-resolution frequency counters like the Agilent 53131/2A and Agilent 53230A. For precise frequency measurements of the SiT15xx family of micro-power 32 kHz oscillators, the frequency counter must have either a high stability OCXO reference or be disciplined by GPS or Rubidium clock reference. For other instruments, like time interval analyzers or simple counters, a gate time of 1 sec or higher is recommended. For details refer to application note32kHz SIT15xx振荡器的测量指南。

Typical no load operating supply current of a SiT15xx device is around 850 nA at room temperature depending on the voltage swing of the output stage. When measuring supply current down to the nano-amp range, a high-resolution digital ammeter similar to an Agilent 34401A must be used. For details refer to the application note32kHz SIT15xx振荡器的测量指南。

可以在应用笔记中找到CSP包的布局建议Best Design and Layout Practices。The manufacturing guidelines are listed on page 10 of theSiT1532 data sheet。

2012年包的布局建议可以在应用笔记中找到Best Design and Layout Practices。The manufacturing guidelines are listed on page 9 of theSIT1533数据表。

Our ultra-performance single-endedSiT820x家庭和差分结束SiT912xfamilies offer the best jitter margin as reference clocks for the following serial interfaces.

• USB 2.0.
• PCIe 1.0, PCIe 2.0, PCIe 3.0
• SAT-2, SAT-3
• SAS, SAS-2, SAS-3
• 1, 10 and 40 GbE
• 1GFC, 2GFC, 4GFC

For applications that are power sensitive, our low power single-ended oscillator familiesSIT1602.,SIT8008/9,SIT1618,SiT891x,SiT892xare recommended for the following interfaces.

• USB 2.0.
• SAT-2, SAT-3
• SAS, SAS-2, SAS-3
• EPON
• 1 GbE

Peak-to-peak cycle-to-cycle jitter (C2C) can be calculated from the period jitter (PerJ) spec specified in the datasheet as follows.
C2C_rms =√3* PerJ_rms
C2C_p-p = 2 * 3.09 * C2C_rms, for 1000 samples

For example: peak-to-peak C2C jitter for SiT9120 would be 12.8 ps p-p typical and 18.2 ps p-p max.

You can find phase jitter at most common frequencies in ourOnline Phase Noise and Jitter Calculator。Period jitter at specific supply voltages and output frequencies can be found in SiTime product datasheets. All SiTime devices within the same family will exhibit similar period and phase jitter across all supported frequencies under the same VDD condition. Period and phase jitter values are also provided inFrequency-Specific Test Reports。

sit's相位噪声和抖动计算器所有ows you to calculate integrated phase jitter (RMS) and plot phase noise data.

Phase noise plots are also included in SiTime’sFrequency-Specific Test Reports。

对于在线工具或报告未涵盖的频率，请联系境内销售支持团队（亚博电竞电子邮件要么在线形式) and specify the following.

• Base family part number (SiT1602, SiT820x, etc.)
• Nominal frequency in Hz
• VDD（1.8 / 2.5 / 3.3）在伏特
• 在Hz中启动频率偏移（10,100,1k）

For a quick estimate, use the following equation to derive the phase noise for your specific frequency:

PNs = PNi + 20*Log (Fs/Fi)

哪里;
发布相位噪声的标称频率
Fs – Nominal frequency for which phase noise is requested
PNI发表相位噪声

PNS - 特定标称频率的阶段噪声

In most applications, the LVCMOS oscillator drives capacitive loads. During the rising edges, the device draws current from the power supply to charge up load capacitance. During the falling edges, the capacitance discharges to GND. The average current going through the load depends on the following parameters:

Output frequency (Fout). This determines how often current is drawn from the power supply.

1. Load capacitance value (Cload). Larger capacitance values require more current to charge up load capacitance.
2. Power supply voltage (Vdd). More current is required to charge up the load to higher voltages.

The additional power supply current from the load is computed as below:

I_load = Cload * Vdd * Fout

在F1处的输出频率的NO负载电流消耗可以估计为（1）在数据表中指定的参考频率f0处的负载电流，并且（2）两个频率之间的内部电容上的驱动电流差异，根据以下等式：

IDD_NL_F1 = IDD_NL_F0 + CINT · VDD · (F1 – F0)

哪里：
IDD_NL_F1 : No load current consumption at frequency F1,
IDD_NL_F0 : No load current consumption specified in datasheet at frequency F0,
VDD：电源电压，
CINT：内部电容是：
6.5 PF（典型值）和8 PF（最大值）SIT1602，SIT8008 / 9，SIT1618，SIT8918 / 9，SIT8920 / 1/4 / 5家庭
2208/9，SIT8225，SIT3701，SIT3701，SIT8102，SIT3701，SIT8102家庭

看到table in Appendix C of the application note onTermination Recommendations for Single-ended Oscillator Driving Single or Multiple Loads。

是。sitoscillators are designed with a programmable architecture that enables configuration of several parameters including any output frequency (to six decimals of accuracy), frequency stability (ppm), and supply voltage within the device’s operating range. Additional features such as drive strength can be programmed and functionality of pin 1 can be changed to match application requirements. See the Ordering Information page within product datasheets for details on specification options.

Depending upon quantity and lead-time requirements, SiTime oscillators can be programmed at the factory for production volumes (three to five week lead times), programmed by specific authorized distributors (24 hour lead times), or instantly programmed in the field using aTime Machine IIportable programmer for sample volumes.

这个功能对于大多数SiTime振荡器(销1针) can be programmed to either "output enable" (OE) or "standby" (ST) functions. In both cases, pulling pin 1 Low stops the device's output oscillation, but in two different ways, as described below.

Applying logic Low to the OE pin only disables the output driver and puts it in Hi-Z mode, but the rest of the device is still running. Power consumption decreases due to the inactivity of the output. For example, for a 3.3V SiT8003 20 MHz device, the IDD decreases from 4 mA to 3.3 mA for a 15 pF load. When the OE pin is pulled High, the output typically enables in less than 1 us.

当ST引脚拉低时，具有ST引脚的设备进入待机模式。设备的所有内部电路关闭，电流减小到待机电流，通常在少量微安的范围内。当ST被拉高时，设备通过“恢复”过程，这可能需要3 ms到10 ms。备用电流和恢复时间段是在设备数据表中指定的。一些趋势数据表未具体指定恢复时间;在这些情况下，恢复时间与“启动时间”相同。

是。具有单端LVCMOS输出的频次设备通常指定为15 PF电容负载，用于上升和下降时间。该装置可以驱动更大的负载，高达60 PF，较慢的上升和跌倒时间。对于需要快速上升和跌倒时间（〜1ns）和驱动大电容负载的能力的应用，可根据要求提供具有高驱动强度输出的缓冲器设备。联系sitfor more details.

是。Users may adjust the output buffers of SiTime oscillator by changing the drive current strength. By increasing or decreasing the maximum drive current of the output stage, rise and fall times may be reduced or increased, respectively. A high drive current strength enables faster rise and fall times while driving a larger load. A low drive current strength reduces the clock edge slew rate and reduces potential EMI.

SITIME提供现场可编程振荡器，以便使用Time Machine II, an oscillator programmer that allows users to configure various parameters including rise and fall time.

看到sitdatasheets for more details or contactsitfor ordering parts with modified drive strength.

是。Sitime提供现场可编程振荡器，适用于Time Machine™II，一个完整的便携式编程套件。该工具可以编程频率，电压，稳定性和其他功能特性，例如驱动强度或扩频。程序员和现场可编程设备是通过使用定制频率的即时样本或调节驱动强度来快速原型设计和优化系统性能的理想选择。现场可编程振荡器具有行业标准的脚印，因此它们可以用作遗留石英振荡器的替代品，而无需任何板变化。看到Time Machine II获取详细信息。

sitoffers the following options for in-system programmability:

I2C / SPI振荡器具有差分输出（SiT3951和SiT3552) enable pulling/tuning frequency up to ±3200 ppm via I2C or SPI with 0.005 ppb resolution, offering designers great flexibility.

具有LVCMOS输出的数字控制振荡器（DCXO）（SIT3907.) and differential outputs (SIT3921.和SIT3922）。这些振荡器允许用户在窄范围内（最多±1600ppm）和1 ppb分辨率在窄范围内动态地改变输出频率。

These devices also replace the analog interface in many VCXO applications.

sitMEMS oscillators offer two configurable features that address EMI issues for environmental compliance without requiring any modifications to the PCB design.

1. Programmable Drive Strength
   1. Reducing drive strength increases the rise-fall time of the clock waveform, thereby attenuating the power of EM waves at higher harmonics
   2. The drive strength table in datasheets lists supported drive strengths, achievable rise-fall time for various load capacitances from 5 pf to 60 pf
   3. Effective at mitigating EM sourced from clock trace
2. Spread Spectrum Clocking
   1. Support for center and down spread achieves up to -17 dB attenuation of 3rd harmonic and higher EM waves
   2. 扩频范围：±0.25％至±2％中心，差价-0.5％至4％蔓延
   3. 有效在系统级缓解EM

For more information, seespread spectrum oscillator page要么application notesitSpread Spectrum Clock Oscillators。

Most of MCU and FPGA designs are implemented as synchronous digital blocks. The clock tree for these blocks is derived from a common external clock reference. SiTime recommends using down spread clock sources to ensure that the setup and hold times are not violated across process, VDD, and temperature for the critical timing paths in these blocks.

For more information, seespread spectrum oscillator page要么application notesitSpread Spectrum Clock Oscillators。

sitrecommends a 0.1 uF low ESR multi-layer ceramic chip capacitor placed close to and across the VDD and GND pins for all MHz oscillators.

For < 1 MHz oscillator families (SiT153x, SiT1552 or SiT1630) a bypass capacitor is not required. These families have internal bulk filtering that provides sufficient power supply filtering for noise up to 300 mV peak-to-peak and 10 MHz frequency component.

Both LC and RC filter on VDD can be considered for power supply noise filtering. An LC filter has less voltage drop and is preferred for oscillator families with IDD > 5 mA. An RC filter can be used for oscillators drawing under 5 mA. More details are provided in application noteBest Design and Layout Practices。

不。The operating supply voltage tolerance in the datasheet specifies the DC voltage range to which the device has been characterized. This DC voltage tolerance, typically 10% of nominal VDD, should not be confused with the AC noise ripple on the supply voltage. The capability to reject AC noise from voltage supply is defined by Power Supply Noise Sensitivity (PSNS) which measures the amount of additional jitter induced by the AC noise ripple over a certain power supply noise spectrum range.

In most applications, the LVCMOS oscillator drives capacitive loads. During the rising edges, the device draws current from the power supply to charge up load capacitance. During the falling edges, the capacitance discharges to GND. The average current going through the load depends on the following parameters:

Output frequency (Fout). This determines how often current is drawn from the power supply.

1. Load capacitance value (Cload). Larger capacitance values require more current to charge up load capacitance.
2. Power supply voltage (Vdd). More current is required to charge up the load to higher voltages.

The additional power supply current from the load is computed as below:

I_load = Cload * Vdd * Fout

看到table in Appendix C of the application note onTermination Recommendations for Single-ended Oscillator Driving Single or Multiple Loads。

是。具有单端LVCMOS输出的频次设备通常指定为15 PF电容负载，用于上升和下降时间。该装置可以驱动更大的负载，高达60 PF，较慢的上升和跌倒时间。对于需要快速上升和跌倒时间（〜1ns）和驱动大电容负载的能力的应用，可根据要求提供具有高驱动强度输出的缓冲器设备。联系sitfor more details.

We don’t offer clock fan out buffers. However, our clock driver can be configured to drive multiple loads. For details, refer to application noteTermination Recommendations for Single-ended Oscillator Driving Single or Multiple Loads

不。µ力量的转换速率32 kHz振荡器in the order of 10s of ns. Hence multiple loads at the end of up to 10” traces can be driven without any concern of signal integrity or reflections. For details, refer to application noteDriving Multiple Loads with 32 kHz Nano-Power MEMS Oscillators。